The PRUSS also has a general interrupt controller that allows unification of events from the peripheral, ARM, DSP and PRU cores. The cores do not have a 'commands convey ' instruction or interrupt vector commands for hardware multiplication and division – all interrupts are processed in the mode of scanning via the indicator in one of the registers. These cores have a simplified RISC architecture that supports 40 commands with determined time of execution (1 time unit), making possible enhanced opportunity for handling bits in registers. This subsystem contains two independent 32-bit cores, each with their own instruction sets, independent of either the DSP or ARM cores.
Applications of this subsystem (PRUSS) are diverse, such as implementation of additional interfaces or maintenance of interfaces in order to arrange specific protocols such as in an auxiliary DSP or ARM core.įigure 6 shows the general structure of PRU subsystem (PRUSS). The PRU is based on two 32-bit cores, each with its own memory for storage of commands and data.
In addition to the capabilities discussed in Part 1 in this series, an important feature of the OMAP-L138 SoC family that is of enormous benefit to a developer is the availability of a separate subsystem, the Programmable Real-Time Unit (PRU). Part 2: The Pros and Cons of OMAP's Programmable Real-Time Unit
Windows ce 6.0 skype series#
The authors discuss the pros and cons of the OMAP’s Programmable Real-Time Unit in the second of a three part series on porting the Windows CE 6.0 R2 embedded operating system to the Texas Instruments ARM-based family of OMAP-L138 processors.
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